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Finding all test vectors for a single stuck-at fault
Hi,How can we find all test vectors for a given stuck-at faults? One way is ofcourse, exhaustive verilog simulation wih all possible input vectors. But that quickly becomes impracticalas the number of...
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To find model test parameter
I am working in CADENCE spectra tool. Can any one help me to find model test parameters of UMC180nm as soon as possible.
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Current source equivalent/substitute
Hi,I desgined the circuit attached, but I need to replace the current source with an equivalent circuit using an operational amplifier (with voltage source).The current source is adjustable from 4mA...
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CONFORMAL LEC- MODULES SKIPPED FROM HIER. BCOZ OFEXTRA PORTS AFTER MBIST...
Hi all,I'm doing logical equivalence check between1)RTL n MBIST inserted NETLIST2)PLAIN NETLIST without MBIST n DFT stuffs vs MBIST inserted NETLISTTEST_MODE is a top level pin of my design which when...
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Is it possible for VHDL to use a verilog/systemverilog package ?
Hi all, I want to know if I compile one systemverilog package in a library, then in vhdl side, can it access the element in this package ? For example .//file pkg.svpackage pkg;const int a =10;...
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schedule crash
Hi,i wrote some code in C++ and it is successfully built in CtoS but when I'm trying to schedule the program is crashing.My code is very similar to example: jpeg_idct_tutorial and I'm doing everything...
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Font size of C-to-Silicon GUI
Hi!I am running C-to-Silicon on CentOS 6.3.Currently the fonts of menu bars are too small for being easy to read. Is there a way for increasing the fonts size? On Google I found some configuration...
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Incisive commands
HiWhat are the equivalent commands in Incisive for the following ModelSim commands:add listconfigure list write list file.txt Thanks
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How to plot current versus voltage curve in waveform graph XL with cadence 6.1.4
Hello !I need to plot a current versus voltage curve (with Waveform Graph XL version Thu Dec 2 23:00:39) after running a transient simulation with cadence version IC6.1.4.500.10I don't find the way to...
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Generate spectre netlist from command line/script
Hi, I would like to find a method of generating spectre netlists using a script, preferably an Ocean script. At present, I have a pile of schematics, which do not have netlists. I can create netlists...
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Regarding Coverage excluding a module
Hi i am MohanI am running, coverage report,, when i it is completed and the coverage report is showing covering all modules. But i don't need some of modules to be covered which this i can improve...
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Resolver Model PSpice
Hello,I am simulating a front-end for an electronic system at pspice.The sensor that I want to use is a Resolver.Does someone knows how can I find (or in the latest build..) a model / library for a...
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Chipware equivalent of DW_fp_log2
Hi Guys, Anyone aware of any CW IP of DW_fp_log2 or any of the DW log function. Do we have any logarithm IP from cadence available to be use instantly.Thanks
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Need help....about schematic and foot print
Hi, I can place the components form the list of library available...but now when i try to export the netlist...they say that they are missing the foot print...dont thay come attached with the library...
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Generate HSPICE subckt from OCEAN
I want to create a subckt HSPICE model for a cell that I have. I have been able to get most of the way to what I want by simply using the following SKILL code:simulator('hspiceD)design("MyLib" "MyCell"...
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PSPice Ftable Parameters
Hi there.I'm developing a circuit in PSpice including an Impedance-model, which is simulated within a real and a complex part. Also can be looked like a Resistor and a Capacitor that change values...
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SystemC sc_method schedule
Hi all, I have a question about systemC sc_method schedule. In my work, event A will trigger sc_method A, event B will trigger sc_method B; and sc_method A and B both will modify a same global...
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Why do I get an error when I try to generate (any) system Verilog module?
If I try to make a new cell view of type system verilog from the library manager GUI I systematically get this error (the content of the module does not matter):F,AMSASV: The -ams and -sv options...
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Simulating Solar cells in PSPICE
Good day everyone,I have some questions regarding simulating solar cells in PSPICE. I am trying to simulate the reverse characteristics of shading on solar cells, but it is difficult for me. I am...
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need solution for following error in cadence RTL synthesis tool
reg [7:0]cb[3:0][3:0]; |Error : Verilog-2001 feature. [VLOGPT-3] [read_hdl] : Multiple dimensions in file './sad.v' on line 8, column 22. : The design must be read...
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