I'm trying to simulate a practice code . Verilog verification of my code do not give any error.But when I try to elaborate, this error is being showed:
ncelab: *E,CUVHNF (./FSM_test.v,17|20): Hierarchical name component lookup failed at 'l'
What does this mean? How can I debug this error ? Is there any archive or list of possible error list so that I don't have to ask in forum to understand the errors.